For example, Japanese Patent Application Laid-Open Publication No. 2009-123967 (Patent Document 1) discloses a method of manufacturing a semiconductor device, wherein a single-crystal silicon layer is epitaxially grown in openings in an oxide film formed in a main surface of a starting substrate, a polycrystalline silicon layer is grown on the oxide film, and defects etc. introduced into the single-crystal silicon layer and the polycrystalline silicon layer are then recovered by thermal treatment or laser annealing treatment.
Japanese Patent Application Laid-Open Publication No. 2009-43952 (Patent Document 2) discloses a method of manufacturing a semiconductor device, wherein a single-crystal thin film is formed in an active portion by epitaxial growth from second openings provided in a substrate oxide film, third openings corresponding to the second openings of the substrate oxide film are then formed in the single-crystal thin film, and the interiors of the third openings are buried again with an insulating film.
Japanese Patent Application Laid-Open Publication No. 2008-153454 (Patent Document 3) discloses a method of manufacturing a MOS-type semiconductor device including: a step of forming a second insulating film in a first opening formed in a main surface of a semiconductor substrate and forming a second opening in the second insulating film; a step of forming a cathode film by forming a first cathode film burying part of the first opening and forming a second cathode film burying the rest of the first opening; and a step of forming a gate insulating film and a gate electrode on the surface of the cathode film and then forming a base region and an emitter region in the first cathode film by ion implantation, wherein the first cathode film is formed by an epitaxial method.
Japanese Patent Application Laid-Open Publication No. 2008-532257 (Patent Document 4) discloses a semiconductor device, wherein latch-up is prevented by providing a buried insulating region partially between an n−-drift layer and a first n-region thereabove, depletion of the n−-drift layer in an off-state is facilitated by providing a p-region between the buried insulating region and the n−-drift layer, and the heat generated in a channel region or the first n-region can be allowed to escape to a p+-collector layer, which is a semiconductor substrate, by providing a second n-region between the first n-region and the n−-drift layer.
Japanese Patent Application Laid-Open Publication No. 2007-42826 (Patent Document 5) discloses a semiconductor device, wherein a Box layer is bored at a location close to a scribe line of a diode active region and an edge region, and a p−-buried region in contact with the Box layer is formed at an end of the Box layer in the diode active region side so as to reduce electric-field concentration and ensure a high withstand voltage.
Japanese Patent Application Laid-Open Publication No. 2001-515662 (Patent Document 6) discloses an SOI-IGBT, wherein a channel zone, a cell zone, and an intermediate zone are formed on an insulating layer provided on a semiconductor substrate and are connected to the semiconductor substrate via cut-away parts formed in the insulating layer.
Japanese Patent Application Laid-Open Publication No. H9-270513 (Patent Document 7) discloses a power device such as a power MOSFET having a high avalanche breakdown voltage obtained by burying an oxide film in an element and proactively utilizing an SOI structure.
Japanese Patent Application Laid-Open Publication No. H11-195784 (Patent Document 8) discloses an insulating-gate-type semiconductor element having a structure in which: gate electrodes with gate insulating films are disposed in a base region so as to narrow a carrier diffusion path, emitter regions are provided at both ends on the upper side of the gate insulating films, holes which have passed through the diffusion path easily gather in the emitter regions and do not easily gather in the emitter region of a parasitic transistor, and the resistance of the base region is reduced.
Japanese Patent Application Laid-Open Publication No. H9-331063 (Patent Document 9) discloses a gate-trench-type high withstand voltage IGBT, wherein an insulating layer is buried in a region of an n−-silicon substrate between gate trenches disposed at a predetermined pitch.
Japanese Patent Application Laid-Open Publication No. 2002-158356 (Patent Document 10) discloses a MIS semiconductor device such as an IGBT which enables miniaturization, etc. of an emitter structure by forming gate electrodes on a semiconductor substrate via an insulating film and forming p-base regions and n+-emitter regions in a thin-film semiconductor layer formed, via the insulating film, on the gate electrodes from the surface of the semiconductor substrate and through a coupling semiconductor part and causing an emitter layer to be a thin film.
Japanese Patent Application Laid-Open Publication No. 2010-62262 (Patent Document 11) discloses an IGBT having: a base layer; a buried insulating film having an opening; a surface semiconductor layer connected to the base layer below the opening; a p-type channel formation layer, an n+-type source layer, and a p+-type emitter layer formed in the surface semiconductor layer; a gate electrode formed on the surface semiconductor layer via a gate insulating film; an n+-type buffer layer; and a p-type collector layer, etc., wherein the content that the thickness of the surface semiconductor layer is 20 to 100 nm is described.